Power saving is getting more and more important in recent integrated circuit design for all portable applications (for example, PDA, laptop computer, cellular phone . . . etc.). The power consumption can be categorized into two main categories: dynamic power consumption (switching power, P=CV2f), and static (leakage) power consumption.
For the dynamic power consumption, two techniques have been applied to reduce the power consumption by reducing C, V, and/or f (total capacitance, supplied voltage and/or operation frequency):                1. Improve processing technology, so both the supplied voltage and the circuit area/capacitance are reduced (reducing C and V).        2. Gated clock. Turn off the clock to reduce the switching frequency (reducing f).        
For the static (leakage) power consumption, following methods have been used:                3. Devices/circuit improvement. In deep sub-micron and portable circuit design, the leakage current becomes a major factor in power consumption. Designers use high cut-in voltage (VT) devices to reduce the leakage current and to improve static power consumption.        4. Gated power. Turn off the power for circuits not in use.        
As to the method 3 stated above, a high VT might increase short circuit current, which may consume more dynamic power. Moreover, methods 1 and 3 must improve the process technologies, are expensive and progress slowly. Most of the fabless IC design houses could not afford the expenses and the developing time, so use whatever existing technologies to meet the power budget, methods 2 and 4 are fully controllable for the fabless design houses. Method 2 is considered as a better solution for the dynamic power saving, and method 4 is considered as an optimal solution for decreasing the leakage current.
For method 2, it's well known and has been widely used. There are CAD tools supporting the gated clock technology (for example, Synopsys' Power Compiler).
For a portable device more than 95% of the mission time is in the standby mode, so leakage current is one of the dominant factors for the power consumption. But the leakage current could not be blocked by gated clock (method 2). Gated power, method 4, is the best solution for portable devices' static power reduction. However, method 4 of gated power has not been widely used, because of the following two reasons:                1. Gated power needs extra memories, control circuits, and routing wires to save the contents of a power-off block. Too much hardware overheads are involved.        2. The power-off/power-on sequences are very trivial.        
With two disadvantages stated above, gated power are widely known but not used often, so there are rooms for providing improvement.